The present disclosure relates to an adaptive bias circuit and a power amplifier.
In accordance with the development of the Information Technology (IT) industry, demand for wireless transceivers capable of transmitting and receiving mass amounts of information has gradually increased. In addition, wireless transceivers that are cheap, consumes relatively low amounts of power, and have high performance have been demanded.
In such wireless transceivers, there is a trend for a majority of internal circuit blocks to be integrated in a single chip using complementary metal oxide semiconductor (CMOS) process technology. However, to date, only power amplifiers have been able to be implemented using indium gallium phosphide (InGaP)/gallium arsenide (GaAs) hetero-junction bipolar transistor (HET) process technology, a compound semiconductor process technology, due to a problem with CMOS process technology itself.
In compound semiconductor process technology such as InGaP/GaAs HBT process technology, manufacturing costs of a device are higher, as compared with CMOS process technology, and devices should be formed to have a multi-chip structure, whereby it maybe difficult to couple such devices to a circuit block implemented by the CMOS process in order to improve linearity. For this reason, there are limitations in decreasing manufacturing costs for wireless transceivers. Therefore, research into CMOS process-based power amplifiers has been demanded.
In addition, in accordance with the implementation of high levels of integration of wireless transceivers, integration of transmitting and receiving ends as well as front ends has been demanded. Therefore, in order to implement a system on chip (SoC), it is necessary to stabilize all biases of power amplifiers.
Meanwhile, as a bias circuit providing a bias voltage to an existing power amplifier, an adaptive bias circuit capable of controlling a bias voltage depending on an envelope of an input signal has been used.
Such an adaptive bias circuit includes an envelope amplifying circuit in order to detect and amplify the envelope of the input signal. The envelope amplifying circuit includes two transistors stacked between a terminal receiving VDD, a power supply voltage, and a terminal receiving VS, a source voltage.
Here, since VDD and VS are supplied using a separate power supply circuit present outside of the power amplifier, it may be relatively complicated to implement the circuit and the circuit may be affected by external factors, such that the source voltage may be changed due to an influence from the outside. In the case in which the source voltage is changed, an operation of the envelope amplifying circuit sensitive to changes in the source voltage may become unstable.
The following Related Art Document (Patent Document 1), which relates to an amplifier using a dynamic bias, does not disclose a technical feature of providing a source voltage of a bias circuit using a power supply voltage of the bias circuit in order to stabilize a bias voltage.
[Related Art Document]
(Patent Document 1) Japanese Patent Laid-Open Publication No. 2013-123237